1. Technical Field of the Invention
The present invention relates to a divider, and more particularly to a high frequency 3-phase-selection fractional-N divider.
2. Discussion of Related Art
Phase-Locked Loops (PLLs) find application in various context where a stable, often high frequency, clock signal is desired. Applications of PLLs include, for example, clock generation for CPUs and for telecommunications. Often, PLLs are required to operate at high frequencies.
PLLs often need fractional-N feedback dividers, especially some given fraction feedback dividers such as (N+⅓) or (N+⅔). A divide-by-(N+⅓) or (N+⅔) is often utilized in computer clock products, for example. However, general methods of implementing fractional-N dividers such as a sigma-delta arithmetic divider, for example, are complicated for a given fraction and may occupy a large number of logic circuits within an integrated circuit to implement.
Therefore, there is a need for fractional feedback dividers that are easily implemented and require fewer logic circuits.